DIYALA JOURNAL OF ENGINEERING SCIENCES

The escalating dependence on artificial intelligence (AI) within the healthcare sector presents significant challenges pertaining to data privacy, regulatory adherence, and the pragmatic implementation of predictive models. This review meticulously examines the amalgamation of Federated Learning (FL) and Differential Privacy (DP) as a prospective framework to mitigate these issues within decentralized healthcare infrastructures. We conduct a comprehensive analysis of extant FL-DP frameworks, concentrating on their capacity to safeguard privacy, uphold performance standards, and function efficiently in real-time clinical settings. The review encompasses architectural advancements, edge computing methodologies, adaptive privacy budgets, and the contributions of blockchain and the Internet of Medical Things (IoMT) in facilitating secure data interchange. Comparative assessments and case studies are synthesized to evaluate model precision, scalability, and conformity with regulatory mandates. Notwithstanding significant advancements, we delineate critical deficiencies, including ethical dilemmas, algorithmic equity, data disparity, and obstacles to deployment. Our contributions consist of a benchmarking framework, the delineation of unresolved research inquiries, and actionable insights for the formulation of secure, just, and scalable FL-DP systems within the healthcare domain. This paper delineates a strategic framework for prospective research and the execution of privacy-preserving AI within clinical practice. The outcomes highlight significant potential for real-world clinical implementation, fostering enhanced patient care, supporting regulatory compliance, and enabling scalable, privacy-preserving AI adoption across diverse healthcare environments.

The continuous scaling of MOSFETs to meet the demands of high-performance devices has intensified challenges such as short-channel effects (SCEs), which degrade device reliability and efficiency. To address these issues, this study investigates the influence of SiO₂ buried layer thickness and vertical positioning on the electrical performance of 20 nm n-MOSFETs incorporating a high-k dielectric gate stack. Using TCAD Silvaco ATLAS, the research systematically evaluates how buried oxide thickness (10 nm to 50 nm) and depth (30 nm to direct contact with the channel) affect key device parameters, including threshold voltage (Vth), drain-induced barrier lowering (DIBL), breakdown voltage, ON current (Ion), leakage current (Ioff), and the Ion/Ioff ratio. Results show that increasing the buried layer thickness increases Ioff from 8.51 × 10⁻¹¹ A/m (without buried layer) to 3.09 × 10-10 A/m at 50 nm, while Ion slightly increases to 2.3 × 10⁻³ A/m. Although this reduces the Ion/Ioff ratio from 2.37 × 10⁷ to 7.54 × 10⁶, it also significantly improves breakdown voltage from 85.09 V to 167.4 V at 10 nm thickness. Notably, the breakdown voltage decreases to 76.26 V at 50 nm. In terms of vertical positioning, placing a 10 nm SiO₂ buried layer in direct contact with the channel yields the highest breakdown voltage of 1186.7 V and the lowest Ioff of 5.15 × 10⁻¹¹ A/m, with an Ion/Ioff ratio of 3.62 × 10⁷. These results highlight that both the thickness and position of the buried oxide layer play a crucial role in suppressing SCEs and enhancing breakdown robustness.