Iraqi Journal of Information and communication technology

Most systems of speaker recognition work on speech feature primarily classified of being a low level which considerably relies on speaker physical characteristics and, to the lower extent, the acquired speaking habits .In this paper present a system to recognition and identification in Arabic speaker. It includes two phases (training phase and testing phase) each phase includes the using of audio features (Mean, Standard Division, Zero Crossing ,Amplitude). after get the feature, the recognition step is using (J48, KNN, LVQ),) where the Nearest Neighbor (KNN)applied o get the similarity of the data training and data testing , LVQ neural network used for Speech Recognition and Arabic language Identification. This sentence contains words especially kidnappings and kidnappers are ten sentences and pronounce these sentences by 10 people, five men and five women of different ages and each of the ten pronunciation of all sentences, so a total of 100 samples and the samples were recorded on audio and wave. The results of the sentences pronounced by women are higher than the results of the same sentences pronounced by men. They achieved better recognition rate 85, 93, 96.4%

Sparse Code Multiple Access (SCMA) is one of the Non- Orthogonal Multiple Access (NOMA) that attracts many researchers for its promising future uses in 5G systems. In this paper, a Computer Generated-Sparse Code Multiple Access (CG-SCMA) is proposed. CG- SCMA generates a complex SCMA codebook that maximizes the Minimum Euclidian Distance (MinED) of 16- point star-Quadrature Amplitude Modulation (QAM).This codebook is generated using computer program to specify the most appropriate values for this constellation, followed by Trellis Coded Modulation(TCM) which is used to divide the constellation into four sub constellations to maximize Min ED. The new codebook reaches MinED equal to 3.46, 2.16, 2.16, 3.46 for the four sub constellations sequentially. This achieves increment over SCMA codebook based on 16- point star-QAM by 10.1%. The multiplexer and de-multiplexer of both proposed codebook and traditional SCAM codebook is hardware implemented by Field Programmable Gate Array(FPGA)using net FPGA- 1G- CML Kintex-7. The achievements of this work is speeding up the process by 597.6 times over MATLAB simulator and decrease Bit Error Rate(BER) compared to open literature codebooks

Network attacks are classified according to their objective into three types: Denial of Services (DOS),reconnaissance and unauthorized access. A base signature Intrusion Detection System (IDS) which gives an alarm when the monitor network traffic meets a previously specified set of criteria of attack traffic. This paper will focus on design, compose, and process IDS rules, and then to decide whether that packet is intrusive or not, by examining the signatures of the attacks in both incoming packets headers and payload to networks. Packet sniffer is performs capturing, decoding and reassembling of the network packet traffic, then passes it to the programmed rules. Linux backtrack tools was used to implement an IDS scenario for two types of attacks (Reconnaissance and Un authorized access). The results show that IDS rules are able to detect large numbers of various attacks

A fully homomorphic encryption (FHE) scheme is considered as a major cryptographic tool in a secure and reliable cloud computing environment, as it enables arbitrary arithmetic processing of a ciphertext without revealing the plaintext. However, due to the very high computation of fully homomorphic encryption system, it stays impractical and unfit for real- time applications. One way to address this restriction is by using graphics processing units (GPUs) and field programmable gate arrays (FPGAs) to implement homomorphic encryption schemes. This paper presents the hardware implementation of enhancement van Dijk, Gentry, Halevi and Vaikuntanathan’s (DGHV 10) scheme over the integer using FPGA technology for high speed computation and real time results. The proposed method was simulated via Vivado system generator tools and implemented in FPGA hardware successfully using NEXYS 4 DDR board with ARTIX 7 XC7A100T . The experimental results show that the FPGA-based fully homomorphic encryption system is 63 times faster than the simulated version of the proposed algorithm