Engineering and Technology Journal

This work presents a comprehensive and comparative study on reconfigurable/tunable microstrip filters, aiming to analyze and understand the impact of varactors, PIN diodes, lumped capacitors, and inductors on the overall filter performance. The study begins by thoroughly classifying reconfigurable microstrip filters based on their reconfigurability functions and the utilization of varactors or PIN diodes. The investigation delves into the influence of varactors and PIN diodes on the performance parameters of microstrip filters. The analysis includes key aspects like center frequency tunability, bandwidth adjustment, and signal attenuation. Additionally, the impact of these reconfigurable elements on insertion loss and return loss is studied to provide a holistic understanding of their role in filter design. Furthermore, the research investigates the interaction between capacitors and inductors in conjunction with varactors and PIN diodes, aiming to clarify their combined effects on filter characteristics. The study involves theoretical modeling and practical experimentation to validate the proposed concepts and results by offering two band stop filters. Accordingly, the first design was implemented to operate at a frequency of 2.4 GHz. In contrast, the second filter involves the realization of two distinct frequencies: an odd-mode frequency of 3.5 GHz and an even-mode frequency of 2.4 GHz. The outcomes of this research are to provide useful insights and guidelines for RF engineers and researchers involved in developing reconfigurable/tunable microstrip filters.

The complexity of hardware realization for the Bell function forces most researchers to replace it with trapezoidal, negatively affecting accuracy. The implementation complexity of the Bell function on FPGA comes from bundling the division operator by FPGA. This requires large hardware resources due to the limited number of logic elements in FPGA devices, such as Lock-Up Tables (LUTs), slices, and DSP48 units, specifically when utilizing the Spartan-3A DSP sc3sd3400a Xilinx FPGA kit. This work investigates hardware resource minimization of Bell Membership Functions (MFs) based on FPGA implementation. A comparative analysis of seven proposed designs with a predesigned system is studied, focusing on resource utilization and performance evaluation. Approach 1 uses the highest number of DSP48 blocks (10). Conversely, Approach 7 achieves the highest area minimization, using the least number of slices (79) and LUTs (144) with zero DSP48 blocks with a reduction rate equal to (97.7%) for slices and (96.7%) LUTs regarding previous work. The absence of multiplication blocks for implementing Approach 7 comes from modifying the precomputation method using half memory size. Performance evaluation indicates varying error rates of 1.06%, 1.14%, and 1.16% for Approaches 1, 2, and 3, respectively. Approaches 6 and 7 exhibit the lowest error rates (0.17%), suggesting superior accuracy, including the previous work. To sum up, the modification in Approach 7 is a very useful method that reduces the hardware platform area and enhances the performance. Thus, this approach is adopted as the best method for designing the Bell function by FPGA.

During the communication system development over the years, detecting and identifying the signal from the affected noise had the major role and the most attention from the researchers. The deep learning algorithm has become a very attractive tool for distinguishing between signal and noise. Learning and training are the two important steps in designing any deep learning system. The proposed system depends on the support vector machine (SVM). The SVM is one of the most popular learning algorithms in different fields, such as signal processing, image processing, communication, and pattern recognition. The SVM classifier is a supervised learning algorithm that uses the closest data points as "support vectors" to build a hyperplane that divides classes. SVM is used to identify the large RADIOML 2018.01A dataset with various signal schemes. The paper strongly emphasized extracting the dataset's most essential features, which improved Support Vector Machines’ capacity to detect signals in noisy and complicated situations. The measured accuracy for the SVM classier for QPSK, 8PSK, and 16 QAM equals 99.7%, 99%, and 99.6%, respectively. The final measured results show the proposed detection system's correctness, robustness, and flexibility based on utilizing the Support Vector Machines (SVM) classifier; this classifier approves its efficacy in signal detection.

One of the challenging aspects of robot navigation is path planning in a dynamic environment. The Q-learning algorithm is one of the reinforcement learning techniques that can be applied to the path planning of a mobile robot. The vital algorithm for any intelligent mobile robot is path planning. On the other hand, the traditional Q-learning method examines every conceivable state of the robot to choose the optimal path. As a result, this method is very computationally intensive, especially when there is a need to compute a large environment. This study proposes a modified version of the technique for planning robot paths. Using the learning rate (1-α) instead of the certification discount factor (γ), the algorithm became completely dependent on the reliance parameters, making it one of those that depend on a single parameter. This reliance can reduce the number of parameters and increase the algorithm’s execution efficiency. A modified version of Q-learning was investigated with to determine the optimal path planning in several dynamic obstacle environments. Learning efficiency was enhanced by using priority trial replay in the improved Inclined Eight Connection Q-learning Algorithm (I8QA). A simulated environment was used for the suggested method, and it was shown that it can successfully plan optimal paths in dynamic obstacle environments. Overall, Q-learning, a strong and adaptable reinforcement learning method, is utilized for dealing with a wide range of problems. The improvement ratio of path length in the experiment environment is 40.812%, indicating that the I8QA algorithm is more compatible with dynamic environments.