Abstract
With the evolution of electronics today, a MOSFET transistor is useful in many applications such as computers due to several advantages. In this research, an NMOS transistor differential amplifier circuit with a passive load that uses a modified Wilson current mirror as a biasing circuit is analyzed, designed, and implemented. The width-to-length ratios of transistors are calculated by considering the voltage and current values at the output of the biasing circuit, and parameters such as conduction parameter, base width modulation parameter, and threshold voltage. A MATLAB version 8.1.0.604(R2010a) programming tool is employed for calculations and the simulations are carried out via Multisim 9 software tool. The output resistance obtained for the current mirror is 2.297 "MΩ". CMRR, output resistance, and power dissipation for differential amplifier circuit are 33.351 "dB", 61.274 "kΩ" and 6.66 "mW", respectively. The results show that the width-to-length ratio, differential gain, and common-mode rejection ratio are decreased with decreasing applied voltage at the output of the biasing circuit while approximately the same values were obtained for output resistance and common-mode gain. The results show a good agreement between the measured values from simulation and the calculated one from design.
Keywords
Common Mode Rejection Ratio
Current Mirror
Differential Pair
NMOS Transistor